The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. Because of the highprecision required in the production of these integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures being created on the wafer surface. As the size of the integrated circuits continues to decrease and the density of microstructures on an integrated circuit increases, the need for precise wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
For a discussion of chemical mechanical planarization (CMP) processes and apparatus, see, for example, Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Arai, et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July, 1994; Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; and Karlsrud et al., U.S. Pat. No. 5,498,199, issued March, 1996.
Such polishing is well known in the art and generally includes attaching one side of the wafer to a flat surface of a wafer carrier or chuck and pressing the other side of the wafer against a flat polishing surface. In general, the polishing surface comprises a horizontal polishing pad that has an exposed abrasive surface of, for example, cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives. Polishing pads can be formed of various materials, as is known in the art, and which are available commercially. Typically, the polishing pad may be a blown polyurethane, such as the IC and GS series of polishing pads available from Rodel Products Corporation in Scottsdale, Ariz. The hardness and density of the polishing pad depends on the material that is to be polished.
During the polishing or planarization process, the workpiece or wafer is typically pressed against the polishing pad surface while the pad rotates about its vertical axis. In addition, to improve the polishing effectiveness, the wafer may also be rotated about its vertical axis and oscillated back and forth over the surface of the polishing pad. It is well known that polishing pads tend to wear unevenly during the polishing operation, causing surface irregularities to develop on the pad. To ensure consistent and accurate planarization and polishing of all workpieces, it is desirable to remove these irregularities.
A well prepared polishing pad facilitates the uniform, high-precision planarization of workpieces. This is particularly important when polishing down the metallic layers to reach the oxide layer on a semiconductor wafer during the manufacture of integrated circuit chips.
Presently known methods for measuring the thickness of an oxide layer on a semiconductor wafer involve measuring the total thickness of an applied oxide layer, determining the desired thickness of the oxide layer after planarization, calculating the pressure to be applied during the polishing or planarization process, and further calculating the approximate time required to remove a predetermined amount of oxide layer for a given pressure and slurry combination. Once the desired removal rate (often expressed in angstroms per minute) is ascertained, a statistical inference is employed to determine the approximate amount of time to remove a desired amount of material. After the wafers have undergone planarization for an amount of time calculated to remove a desired thickness of the oxide layer, the workpieces are removed from the machine and the actual thickness of the oxide layer is measured, for example, through the use of laser interferometric techniques. If it is determined that the oxide layer is still too thick after initial planarization, the workpieces must be reinstalled onto the CMP machine for further oxide layer removal. If, on the other hand, an excessive amount of oxide layer has been removed, it may be necessary to scrap the disks, resulting in substantial unnecessary costs.
Further, the methods of calculating oxide layer thicknesses currently known in the art are principally useful for non-patterned wafers, and generally do not work well on wafers having a substantially repeating surface pattern.
Other techniques may be employed to determine when the layer of tungsten, or other metallic material, has been removed from the oxide layer. Prior art methodologies detect the change in polishing pad motor current, which typically changes in response to the exposure of different semiconductor layers. However, this technique is of limited utility where different slurries and other consumable sets are used during the polishing process. In particular, false trigger may result from an increase or decrease in the surface friction caused by a change in the slurry characteristics rather than by a change in the exposed layer composition. False triggers may also be caused by noise inherent in the polishing system.
Accordingly, a technique is needed which accurately measures the oxide layer (and particularly the end point) thickness which overcomes the shortcoming of the prior art. In addition, a technique is needed which accurately detects the removal of a conductor or semiconductor layer from the oxide substrate layer.